1.Fix bugs when detecting ways value of JZ4775's L2 cache. 2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Reviewed-by: Paul Cercueil <[email protected]> --- Notes: v1->v2: 1.Add corrections to JZ4775's L2 cache ways parameter. 2.Add Paul Cercueil's Reviewed-by. arch/mips/mm/sc-mips.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 97dc0511e63f..dd0a5becaabd 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void) * contradicted by all documentation. */ case MACH_INGENIC_JZ4770: + case MACH_INGENIC_JZ4775: c->scache.ways = 4; break; @@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void) * but that is contradicted by all documentation. */ case MACH_INGENIC_X1000: + case MACH_INGENIC_X1000E: c->scache.sets = 256; c->scache.ways = 4; break; -- 2.11.0
