The following commit has been merged into the timers/core branch of tip: Commit-ID: 51b705af287d08192140d6caf16d64e32a7abfe4 Gitweb: https://git.kernel.org/tip/51b705af287d08192140d6caf16d64e32a7abfe4 Author: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> AuthorDate: Wed, 15 Jul 2020 12:08:55 +01:00 Committer: Daniel Lezcano <daniel.lezc...@linaro.org> CommitterDate: Thu, 24 Sep 2020 10:51:04 +02:00
dt-bindings: timer: renesas,cmt: Document r8a774e1 CMT support Document SoC specific bindings for RZ/G2H (r8a774e1) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be> Acked-by: Rob Herring <r...@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org> Link: https://lore.kernel.org/r/1594811350-14066-6-git-send-email-prabhakar.mahadev-lad...@bp.renesas.com --- Documentation/devicetree/bindings/timer/renesas,cmt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml index 762b650..428db3a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml @@ -71,6 +71,7 @@ properties: - renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M - renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N - renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E + - renesas,r8a774e1-cmt0 # 32-bit CMT0 on RZ/G2H - renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3 - renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W - renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N @@ -85,6 +86,7 @@ properties: - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N - renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E + - renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H - renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3 - renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W - renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N
