According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. So this patch fixes it.
Signed-off-by: Nicolin Chen <[email protected]> --- drivers/memory/tegra/tegra210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 7fb8b5438bf4..088814279616 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .bit = 1, }, .la = { - .reg = 0xb98, + .reg = 0x3e0, .shift = 16, .mask = 0xff, .def = 0x80, -- 2.17.1
