On 23-10-20, 16:24, Hector Yuan wrote: > From: "Hector.Yuan" <hector.y...@mediatek.com> > > Add devicetree bindings for MediaTek HW driver. > > Signed-off-by: Hector.Yuan <hector.y...@mediatek.com> > --- > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 46 > ++++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > diff --git > a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > new file mode 100644 > index 0000000..a99f44f > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek's CPUFREQ Bindings > + > +maintainers: > + - Hector Yuan <hector.y...@mediatek.com> > + > +description: > + CPUFREQ HW is a hardware engine used by MediaTek > + SoCs to manage frequency in hardware. It is capable of controlling > frequency > + for multiple clusters. > + > +properties: > + compatible: > + const: mediatek,cpufreq-hw > + > + reg: > + minItems: 1 > + maxItems: 2 > + description: | > + Addresses and sizes for the memory of the HW bases in each frequency > domain. > + > +required: > + - compatible > + - reg > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpufreq_hw: cpufreq@11bc00 { > + compatible = "mediatek,cpufreq-hw"; > + reg = <0 0x11bc10 0 0x8c>, > + <0 0x11bca0 0 0x8c>; > + }; > + };
You still need to keep the CPU specific part here and explain how this block is going to get used using the other binding you added. -- viresh
