On Fri, Oct 23, 2020 at 1:57 AM Kishon Vijay Abraham I <[email protected]> wrote: > > Hi Nadeem, > > On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote: > > Hi Kishon, > > > >> -----Original Message----- > >> From: Kishon Vijay Abraham I <[email protected]> > >> Sent: Monday, October 19, 2020 10:59 AM > >> To: Athani Nadeem Ladkhan <[email protected]>; > >> [email protected]; [email protected]; [email protected]; linux- > >> [email protected]; [email protected]; Tom Joseph > >> <[email protected]> > >> Cc: Swapnil Kashinath Jakhade <[email protected]>; Milind Parab > >> <[email protected]> > >> Subject: Re: [PATCH v3] PCI: cadence: Retrain Link to work around Gen2 > >> training defect. > >> > >> EXTERNAL MAIL > >> > >> > >> Hi Nadeem, > >> > >> On 30/09/20 11:51 pm, Nadeem Athani wrote: > >>> Cadence controller will not initiate autonomous speed change if > >>> strapped as Gen2. The Retrain Link bit is set as quirk to enable this > >>> speed > >> change. > >>> > >>> Signed-off-by: Nadeem Athani <[email protected]> > >>> --- > >>> Changes in v3: > >>> - To set retrain link bit,checking device capability & link status. > >>> - 32bit read in place of 8bit. > >>> - Minor correction in patch comment. > >>> - Change in variable & macro name. > >>> Changes in v2: > >>> - 16bit read in place of 8bit. > >>> drivers/pci/controller/cadence/pcie-cadence-host.c | 31 > >> ++++++++++++++++++++++ > >>> drivers/pci/controller/cadence/pcie-cadence.h | 9 ++++++- > >>> 2 files changed, 39 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c > >>> b/drivers/pci/controller/cadence/pcie-cadence-host.c > >>> index 4550e0d469ca..2b2ae4e18032 100644 > >>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c > >>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c > >>> @@ -77,6 +77,36 @@ static struct pci_ops cdns_pcie_host_ops = { > >>> .write = pci_generic_config_write, > >>> }; > >>> > >>> +static void cdns_pcie_retrain(struct cdns_pcie *pcie) { > >>> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; > >>> + u16 lnk_stat, lnk_ctl; > >>> + > >>> + if (!cdns_pcie_link_up(pcie)) > >>> + return; > >>> + > >> > >> Is there a IP version that can be used to check if that quirk is > >> applicable? > > There is no such provision.
Cadence just gives out unversioned IP? There may not be s/w readable version, but there's still a version. Look at DWC. > hmm okay. Can we add a DT property to indicate the quirk then since > AFAIK this is not required in future revisions of IP. No, add a driver quirk flag, but set flag that based on compatible strings. > >>> + /* > >>> + * Set retrain bit if current speed is 2.5 GB/s, > >>> + * but the PCIe root port support is > 2.5 GB/s. Though wouldn't setting the retrain bit be harmless even if not needed? Rob
