Tegra194 has 2 QSPI controllers.

This patch adds DT node for these 2 QSPI controllers.

Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi 
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 25f36d6..852980f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -609,6 +609,34 @@
                        status = "disabled";
                };
 
+               spi@3270000 {
+                       compatible = "nvidia,tegra194-qspi";
+                       reg = <0x3270000 0x1000>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&bpmp TEGRA194_CLK_QSPI0>,
+                                <&bpmp TEGRA194_CLK_QSPI0_PM>;
+                       clock-names = "qspi", "qspi_out";
+                       resets = <&bpmp TEGRA194_RESET_QSPI0>;
+                       reset-names = "qspi";
+                       status = "disabled";
+               };
+
+               spi@3300000 {
+                       compatible = "nvidia,tegra194-qspi";
+                       reg = <0x3300000 0x1000>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&bpmp TEGRA194_CLK_QSPI1>,
+                                <&bpmp TEGRA194_CLK_QSPI1_PM>;
+                       clock-names = "qspi", "qspi_out";
+                       resets = <&bpmp TEGRA194_RESET_QSPI1>;
+                       reset-names = "qspi";
+                       status = "disabled";
+               };
+
                pwm1: pwm@3280000 {
                        compatible = "nvidia,tegra194-pwm",
                                     "nvidia,tegra186-pwm";
-- 
2.7.4

Reply via email to