On Thu, Jan 7, 2021 at 2:57 PM Atish Patra <atish.pa...@wdc.com> wrote: > > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock > allocation if it is requested to be aligned with SMP_CACHE_BYTES. > > Signed-off-by: Atish Patra <atish.pa...@wdc.com>
Looks good to me. Reviewed-by: Anup Patel <a...@brainfault.org> > --- > arch/riscv/include/asm/cache.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > index 9b58b104559e..c9c669ea2fe6 100644 > --- a/arch/riscv/include/asm/cache.h > +++ b/arch/riscv/include/asm/cache.h > @@ -7,7 +7,11 @@ > #ifndef _ASM_RISCV_CACHE_H > #define _ASM_RISCV_CACHE_H > > +#ifdef CONFIG_64BIT > #define L1_CACHE_SHIFT 6 > +#else > +#define L1_CACHE_SHIFT 5 > +#endif > > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-ri...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup
