On 28/01/2021 18:20, Peter Zijlstra wrote: > --- a/arch/x86/kernel/hw_breakpoint.c > +++ b/arch/x86/kernel/hw_breakpoint.c > @@ -496,9 +496,32 @@ static int hw_breakpoint_handler(struct > dr6_p = (unsigned long *)ERR_PTR(args->err); > dr6 = *dr6_p; > > - /* If it's a single step, TRAP bits are random */ > - if (dr6 & DR_STEP) > + /* > + * If DR_STEP is set, TRAP bits might also be set, but we must not > + * process them since another exception (without DR_STEP) will follow.
:) How lucky are you feeling? Data breakpoints will in principle merge with DR_STEP (as will all other #DB's with trap semantics), other than the many errata about breakpoints not being recognised correctly. Under VT-x because there is a still unfixed vmexit microcode bug which loses all breakpoint information if DR_STEP is set. %dr6 handling works fine when #DB isn't intercepted, but then you get to keep the pipeline livelock vulnerability as a consequence. Instruction breakpoints on the following instruction will be delivered as a second #DB, because fault style #DBs are raised at a separate position in the instruction execution cycle. ~Andrew
