[PATCH v2 5/8] arm64: dts: imx8mm-nitrogen-r2: add PWMs

[Adrien Grassein]

Add description for the four PWMs.

Signed-off-by: Adrien Grassein <adrien.grass...@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k...@kernel.org>
---
 .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index 8f210e21a1bd..35213f3abecc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -205,6 +205,33 @@ rtc@68 {
        };
 };
 
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&pwm2 {
+       assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
+       assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
+       assigned-clock-rates = <40000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>;
+       status = "okay";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>;
+       status = "okay";
+};
+
+&pwm4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm4>;
+       status = "okay";
+};
+
 /* BT */
 &uart1 {
        pinctrl-names = "default";
@@ -368,6 +395,30 @@ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
                >;
        };
 
+       pinctrl_pwm1: pwm1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
+               >;
+       };
+
+       pinctrl_pwm2: pwm2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
+               >;
+       };
+
+       pinctrl_pwm3: pwm3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
+               >;
+       };
+
+       pinctrl_pwm4: pwm4grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
+               >;
+       };
+
        pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
-- 
2.25.1