[PATCH v2 3/8] arm64: dts: imx8mm-nitrogen-r2: add espi2 support

[Adrien Grassein]

Add the description for espi support.

Signed-off-by: Adrien Grassein <adrien.grass...@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k...@kernel.org>
---
 .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index f62a25efc69e..c4bb22bb4e6a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -10,6 +10,14 @@ / {
        model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
        compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
 
+       clock {
+               clk16m: clk16m {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <16000000>;
+               };
+       };
+
        reg_wlan_vmmc: regulator-wlan-vmmc {
                compatible = "regulator-fixed";
                pinctrl-names = "default";
@@ -38,6 +46,19 @@ &A53_3 {
        cpu-supply = <&reg_buck3>;
 };
 
+/* J15 */
+&ecspi2 {
+       assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
+       assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
+       assigned-clock-rates = <40000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
@@ -270,6 +291,15 @@ &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
 
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x140
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x19
+                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x19
+                       MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x19
+               >;
+       };
+
        pinctrl_fec1: fec1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
-- 
2.25.1