On Mon, 2021-04-19 at 13:23 +0200, Michal Simek wrote: > Hi Marc and Robert, +Anirudha > > On 4/16/21 8:14 PM, Robert Hancock wrote: > > On Fri, 2021-04-16 at 18:53 +0100, Marc Zyngier wrote: > > > On Fri, 16 Apr 2021 17:05:49 +0100, > > > Robert Hancock <robert.hanc...@calian.com> wrote: > > > > On Fri, 2021-04-16 at 14:41 +0100, Marc Zyngier wrote: > > > > > On Fri, 16 Apr 2021 00:32:50 +0100, > > > > > Robert Hancock <robert.hanc...@calian.com> wrote: > > > > > > Previously the XILINX_INTC config option was hidden and only > > > > > > auto-selected on the MicroBlaze platform. However, this IP can also > > > > > > be > > > > > > used on other platforms. Allow this option to be user-enabled. > > > > > > > > > > > > Signed-off-by: Robert Hancock <robert.hanc...@calian.com> > > > > > > > > > > I don't think this is a good idea. In general, people have no idea > > > > > which interrupt controller they need to select. So you either end-up > > > > > with a missing interrupt controller, or a bunch you really don't > > > > > need. > > > > > > > > > > This is essentially a platform constraint, and this should directly > > > > > be > > > > > selected by the platform if you have this IP in your system. > > > > > > > > > > Thanks, > > > > > > > > > > M. > > > > > > > > The problem is essentially that at the platform level, we don't know, > > > > other > > > > than in the MicroBlaze case where we know it will be used as the > > > > platform's > > > > primary interrupt controller. In our case, we are using this IP core on > > > > the > > > > ZynqMP platform as a secondary cascaded interrupt controller in the > > > > FPGA > > > > portion of the device. > > > > But many ZynqMP configurations wouldn't have this device present, it > > > > depends on what the user instantiates in the programmable logic. > > > > Also, this core could just as easily be instantiated in standalone > > > > Xilinx FPGAs which could be connected to many different platforms > > > > over a PCIe, AXI, etc. bus. > > > > > > Not compiling it for some users is great if you happen to *know* what > > > you have to select, which is probably a single digit percentage of the > > > people that build their own kernel. At least having it to depend on > > > ZYNQMP (or some other FPGA platform) would narrow it down. > > > > > > And if you have some other HW in your FPGA, you can make the config > > > fragment for this HW select the right interrupt controller. But I'm > > > definitely not keen on making this a universally user-selectable > > > driver. > > > > In general there is no specific or unique config option for what is > > instantiated in an FPGA, it is completely up to the whims of whoever set it > > up. > > You can instantiate whatever logic cores you want and there is no guarantee > > whether they will or won't end up using this interrupt controller in the > > path > > somewhere, so having a dependency there doesn't make much sense. For FPGA > > logic > > it's ultimately up to the user to ensure the kernel config they are using > > has > > the right drivers enabled for the cores they are using. Kconfig doesn't and > > can't really help in this regard. > > > > There's some precedent on this issue with drivers for various other FPGA- > > based > > IP cores for SPI, I2C, Ethernet etc. Often they started out with an > > architecture constraint which limited them to the platform they were > > originally > > developed with, but which was later removed because the ability to use them > > in > > standalone FPGAs means that the platforms they could potentially be used > > with > > are basically unconstrained. > > > > > > So I don't think having this as a platform constraint makes sense. > > > > > > I don't think imposing this on *everyone*, across all supported > > > architectures and platforms makes any sense. Surely, people who build > > > their own HW (because that's what we are talking about here) can be > > > bothered to add the small Kconfig fragment that is required to their > > > kernel build. > > The same interrupt controller was used by ppc405 and ppc440 xilinx > platform in past. Unfortunately it was separate copy of this microblaze > one and ppc copy should be already removed by removing support for these > platforms. > > The first(default) configuration which was mentioned above is primary > interrupt controller for Microblaze. > > That being said this controller can be used and actually is used by > Xilinx Zynq(arm32) ZynqMP(arm64) and Versal(arm64) SOCs as a cascate > intc controller. I have also seen couple of different cpus in PL which > can use (and actually use it) this soft IP. But limiting it for > Zynq/ZynqMP should be fine. > > Recently my colleague (Anirudha) did some experiments with binding and > unbinding this driver for cases where you are using it as cascade > interrupt controller in a programmable logic(PL) (primary controller is > GIC) and then you want to exchange the whole PL by different > configuration that you need to have option to remove this chip.
It sounds like limiting to Microblaze, Zynq and ZynqMP for now is less controversial and meets our current use case, so will submit v2 with that dependency in place. -- Robert Hancock Senior Hardware Designer, Calian Advanced Technologies www.calian.com
