As described in the commit messages, keep the GDSC configs aligned with
the downstream kernel.
For reference, this was checked using the following code:
To: Bjorn Andersson <anders...@kernel.org>
To: Michael Turquette <mturque...@baylibre.com>
To: Stephen Boyd <sb...@kernel.org>
To: Konrad Dybcio <konradyb...@kernel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delre...@somainline.org>
Cc: ~postmarketos/upstream...@lists.sr.ht
Cc: phone-de...@vger.kernel.org
Cc: linux-arm-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index fa5fe4c2a2ee..049fcbefba50 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -402,7 +402,7 @@ static bool gdsc_get_hwmode(struct generic_pm_domain
*domain, struct device *dev
static int gdsc_init(struct gdsc *sc)
{
- u32 mask, val;
+ u32 mask, val, tmp;
int on, ret;
/*
@@ -420,6 +420,14 @@ static int gdsc_init(struct gdsc *sc)
if (!sc->clk_dis_wait_val)
sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
+ regmap_read(sc->regmap, sc->gdscr, &tmp);
+ if (sc->en_rest_wait_val != ((tmp >> EN_REST_WAIT_SHIFT) & 0xf))
+ printk(KERN_ERR "gdsc_init: %s en_rest_wait_val mismatch: (new)
0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_rest_wait_val, (tmp >>
EN_REST_WAIT_SHIFT) & 0xf);
+ if (sc->en_few_wait_val != ((tmp >> EN_FEW_WAIT_SHIFT) & 0xf))
+ printk(KERN_ERR "gdsc_init: %s en_few_wait_val mismatch: (new)
0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_few_wait_val, (tmp >>
EN_FEW_WAIT_SHIFT) & 0xf);
+ if (sc->clk_dis_wait_val != ((tmp >> CLK_DIS_WAIT_SHIFT) & 0xf))
+ printk(KERN_ERR "gdsc_init: %s clk_dis_wait_val mismatch: (new)
0x%x vs 0x%x (reset)\n", sc->pd.name, sc->clk_dis_wait_val, (tmp >>
CLK_DIS_WAIT_SHIFT) & 0xf);
+
val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
---
Luca Weiss (4):
clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
drivers/clk/qcom/camcc-sm6350.c | 18 ++++++++++++++++++
drivers/clk/qcom/dispcc-sm6350.c | 3 +++
drivers/clk/qcom/gcc-sm6350.c | 6 ++++++
drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++
4 files changed, 33 insertions(+)
---
base-commit: 9c32cda43eb78f78c73aee4aa344b777714e259b
change-id: 20250425-sm6350-gdsc-val-a0162752854f
Best regards,
--
Luca Weiss <luca.we...@fairphone.com>
