Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm: https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
Add device trees for the Kaanapali SoC, MTP (Mobile Test Platform) and QRD (Qualcomm Reference Device), along with the corresponding defconfig and binding, providing initial support to boot to UART shell with UFS enabled. Features added and enabled: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD and regulator - UFS with inline crypto engine (ICE) - LLCC - Watchdog - SD Card - PCIe(enabled on MTP board only) build dependency: - gcc: https://lore.kernel.org/all/[email protected]/ - reviewed - ipcc: https://lore.kernel.org/all/[email protected]/ - reviewed binding dependency: - pdc: https://lore.kernel.org/all/[email protected]/ - reviewed - pcie: https://lore.kernel.org/all/[email protected]/ - reviewed - imem: https://lore.kernel.org/all/[email protected]/ - acked For CPU compatible naming, there is one discussion which is not specific to Kaanapali: https://lore.kernel.org/all/[email protected]/ So it should not block Kaanapali and we keep the "cpu,oryon" compatible here. Signed-off-by: Jingyi Wang <[email protected]> --- Changes in v4: - fix node names in reserved memory - standardize the coding style of 0(0x0 for address, 0x00 for pcie bus range) - Link to v3: https://lore.kernel.org/r/[email protected] Changes in v3: - link bi_tcxo_ao_div2 to gcc node - Dmitry - fix underscores in node names - Dmitry - add reviewed-by tag - Link to v2: https://lore.kernel.org/r/[email protected] Changes in v2: - reorganize patch, merge initial features in one patch - update UFS clocks in GCC - fix nodes order in boards - enable CLK_KAANAPALI_TCSRCC for clk driver change - merge tcsr and tcsrcc nodes - change imem fallback to "mmio-sram" - minor code style fixup - Link to v1: https://lore.kernel.org/r/[email protected] --- Jingyi Wang (5): dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards arm64: defconfig: enable clocks, interconnect and pinctrl for Qualcomm Kaanapali arm64: dts: qcom: Introduce Kaanapali SoC arm64: dts: qcom: kaanapali: Add base MTP board arm64: dts: qcom: kaanapali: Add base QRD board Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 754 +++++++++++ arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 712 ++++++++++ arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1606 +++++++++++++++++++++++ arch/arm64/configs/defconfig | 4 + 6 files changed, 3084 insertions(+) --- base-commit: 4a5663c04bb679631985a15efab774da58c37815 change-id: 20251204-knp-dts-4ad60e175645 prerequisite-change-id: 20251121-gcc_kaanapali-v3-ab91e1065bd4:v5 prerequisite-patch-id: 9a9cd779ee23419a023893f357decbe09da1e42f prerequisite-patch-id: 884f356ecd7f8046636174f56a6485a4be2e5cce prerequisite-patch-id: 0baee9ea7681fe6b4ab1c69f1e087427ad0050e9 prerequisite-patch-id: a7ee79adf85ce9c5aedca168a561a9560fa59b44 prerequisite-patch-id: 0ad500fc45e104a874839181b5ae59a4867ba1cb prerequisite-change-id: 20251021-knp-pdc-395e2100d15f:v2 prerequisite-patch-id: 91797dc6f0e455a546d73254df87fc0ca22aa142 prerequisite-change-id: 20251124-kaanapali-pcie-phy-31968b2b2916:v4 prerequisite-patch-id: 265d61c5de05beea27297c10299239faeef55816 prerequisite-patch-id: 94e3936a21c0e19e5f1990a5cddcb1474b9adc95 prerequisite-patch-id: 69f436a719908a2210b4a4074a0b92bdfef2efd3 prerequisite-patch-id: f0c39c4a4de3b45a66ec8916e8d86a8ad059ade8 prerequisite-patch-id: 389060752aa271d1016ec115f19c0edfd1f831f6 prerequisite-change-id: 20251123-knp-soc-binding-96e2798dcfde:v4 prerequisite-patch-id: 789208c9126c28643c289754cab1681ef3bd396e Best regards, -- Jingyi Wang <[email protected]>
