On 1/16/26 2:38 PM, Luca Weiss wrote:
> Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 194
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 194 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi
> b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 58b4c2966df1..c8771beffa9b 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -1652,6 +1652,72 @@ videocc: clock-controller@aaf0000 {
> #power-domain-cells = <1>;
> };
>
> + cci0: cci@ac15000 {
> + compatible = "qcom,milos-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac15000 0x0 0x1000>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
> + power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "soc_ahb",
> + "cpas_ahb",
> + "cci";
> + pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
With the pins moving to the child nodes, we may as well move the
disablement there, peeking at the code, I think it should handle it
well
[...]
> camcc: clock-controller@adb0000 {
> compatible = "qcom,milos-camcc";
> reg = <0x0 0x0adb0000 0x0 0x40000>;
> @@ -1791,6 +1857,134 @@ tlmm: pinctrl@f100000 {
>
> wakeup-parent = <&pdc>;
>
> + cci0_0_default: cci0-0-default-state {
> + sda-pins {
> + pins = "gpio88";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
It would be fantastic if the GPIOs remained sorted by the GPIO num
Konrad
