Add LPASS LPI pinctrl node required for audio functionality on SM6350. Signed-off-by: Luca Weiss <[email protected]> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi
b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9f9b9f9af0da..b1fb6c812da7 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1448,6 +1448,72 @@ compute-cb@5 {
};
};
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm6350-lpass-lpi-pinctrl";
+ reg = <0x0 0x033c0000 0x0 0x20000>,
+ <0x0 0x03550000 0x0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core",
+ "audio";
+
+ i2s1_active: i2s1-active-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "i2s1_clk";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ ws-pins {
+ pins = "gpio7";
+ function = "i2s1_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio8", "gpio9";
+ function = "i2s1_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2s1_sleep: i2s1-sleep-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "i2s1_clk";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ ws-pins {
+ pins = "gpio7";
+ function = "i2s1_ws";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ data-pins {
+ pins = "gpio8", "gpio9";
+ function = "i2s1_data";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+
gpu: gpu@3d00000 {
compatible = "qcom,adreno-619.0", "qcom,adreno";
reg = <0x0 0x03d00000 0x0 0x40000>,
--
2.52.0
