This commit adds support for HiSilicon CAT/CMT test by adapting the HiSilicon-specificed implementation.
1. Handle Cache Masking on HiSilicon: On HiSilicon's platform, all cache are shareable, platform-level non-contiguous CAT is not applicable, and the test should default to using the full cache. 2. Extend Non-Contiguous CAT Support: HiSilicon always support non-contiguous CBM. 3. Specify Mount Options for HiSilicon resctrlfs: When mounting the resctrl filesystem on HiSilicon platform, specify "l2" option. 4. Adjust Perf Event Attributes for ARM: ARM performance counters do not support mode exclusion. Signed-off-by: Yifan Wu <[email protected]> --- tools/testing/selftests/resctrl/cache.c | 4 +++- tools/testing/selftests/resctrl/cat_test.c | 18 +++++++++++------- tools/testing/selftests/resctrl/resctrlfs.c | 5 ++++- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/resctrl/cache.c b/tools/testing/selftests/resctrl/cache.c index 1ff1104e6575..798aefc6cb29 100644 --- a/tools/testing/selftests/resctrl/cache.c +++ b/tools/testing/selftests/resctrl/cache.c @@ -13,7 +13,9 @@ void perf_event_attr_initialize(struct perf_event_attr *pea, __u64 config) pea->read_format = PERF_FORMAT_GROUP; pea->exclude_kernel = 1; pea->exclude_hv = 1; - pea->exclude_idle = 1; + /* ARM performance counters do not support mode exclusion */ + if (get_vendor() != ARCH_HISILICON) + pea->exclude_idle = 1; pea->exclude_callchain_kernel = 1; pea->inherit = 1; pea->exclude_guest = 1; diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c index f00b622c1460..e5365665a6d3 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -245,11 +245,15 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param ret = get_full_cbm(test->resource, &full_cache_mask); if (ret) return ret; - /* Get the largest contiguous exclusive portion of the cache */ - ret = get_mask_no_shareable(test->resource, &long_mask); - if (ret) - return ret; - + if (get_vendor() == ARCH_HISILICON) { + /* On HiSilicon's platform, all cache are shareable. */ + long_mask = full_cache_mask; + } else { + /* Get the largest contiguous exclusive portion of the cache */ + ret = get_mask_no_shareable(test->resource, &long_mask); + if (ret) + return ret; + } /* Get L3/L2 cache size */ ret = get_cache_size(uparams->cpu, test->resource, &cache_total_size); if (ret) @@ -292,8 +296,8 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test) { unsigned int vendor_id = get_vendor(); - /* AMD and Hygon always support non-contiguous CBM. */ - if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON) + /* AMD and Hygon and HiSilicon always support non-contiguous CBM. */ + if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON || vendor_id == ARCH_HISILICON) return true; #if defined(__i386__) || defined(__x86_64__) /* arch */ diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/selftests/resctrl/resctrlfs.c index 01b775cfe849..7567d3b31efb 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -69,7 +69,10 @@ int mount_resctrlfs(void) return -1; ksft_print_msg("Mounting resctrl to \"%s\"\n", RESCTRL_PATH); - ret = mount("resctrl", RESCTRL_PATH, "resctrl", 0, NULL); + if (get_vendor() == ARCH_HISILICON) + ret = mount("resctrl", RESCTRL_PATH, "resctrl", 0, "l2"); + else + ret = mount("resctrl", RESCTRL_PATH, "resctrl", 0, NULL); if (ret) ksft_perror("mount"); -- 2.33.0
