On Mon, May 18, 2026 at 04:07:29PM +0100, Mark Brown wrote: > The features added by the 2025 dpISA are all straightforward instruction > only features so there is no state to manage, we can just expose hwcaps to > let userspace know they are available. > > F16MM is slightly odd in that the feature is FEAT_F16MM but it is discovered > via ID_AA64FPFR0_EL1.F16MM2. We follow the feature name. > > Signed-off-by: Mark Brown <[email protected]> > --- > Documentation/arch/arm64/elf_hwcaps.rst | 24 ++++++++++++++++++++++++ > arch/arm64/include/uapi/asm/hwcap.h | 8 ++++++++ > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > arch/arm64/kernel/cpuinfo.c | 8 ++++++++ > 4 files changed, 51 insertions(+) > > diff --git a/Documentation/arch/arm64/elf_hwcaps.rst > b/Documentation/arch/arm64/elf_hwcaps.rst > index 97315ae6c0da..07ff9ea1d605 100644 > --- a/Documentation/arch/arm64/elf_hwcaps.rst > +++ b/Documentation/arch/arm64/elf_hwcaps.rst > @@ -451,6 +451,30 @@ HWCAP3_LS64 > of CPU. User should only use ld64b/st64b on supported target (device) > memory location, otherwise fallback to the non-atomic alternatives. > > +HWCAP3_SVE_B16MM > + Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0011 > + > +HWCAP3_SVE2P3 > + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0100 > + > +HWCAP3_SME_LUT6 > + Functionality implied by ID_AA64SMFR0_EL1.LUT6 == 0b1 > + > +HWCAP3_SME2P3 > + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0100 > + > +HWCAP3_F16MM > + Functionality implied by ID_AA64FPFR0_EL1.F16MM2 == 0b1 > + > +HWCAP3_F16F32DOT > + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0010 > + > +HWCAP3_F16F32MM > + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0011 > + > +HWCAP3_SVE_LUT6 > + Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0010 and > + ID_AA64PFR0_EL1.SVE == 0b0001.
I've queued this, but I'm curious why you've called out the 'ID_AA64PFR0_EL1.SVE == 0b0001' part here and not for any of the other SVE caps you're adding? It's also formatted inconsistently from pre-existing entries (such as HWCAP2_SVE_B16B16) which put the ID_AA64PFR0_EL1.SVE part of the antecedent first. Will
