On Sat, 11 Jul 2026 10:23:56 -0500 David Lechner <[email protected]> wrote:
> On 7/10/26 6:20 AM, Rodrigo Alencar via B4 Relay wrote: > > This is the second series of three on updating the AD5686 driver. > > > > Initially, a big patch series was sent: > > https://lore.kernel.org/r/[email protected] > > > > Then, the first patch series added fixes and cleanups: > > https://lore.kernel.org/linux-iio/[email protected]/ > > > > This one is introducing new features: > > - Consume optional reset and correct power supplies; > > - LDAC GPIO handling (active-low, held low when unused); > > - SPI bus sync() implementation for batching multiple transfers; > > - Triggered buffer support, leveraging LDAC and sync() to flush > > all channel writes atomically; > > - Gain control support through the scale property. > > > > Signed-off-by: Rodrigo Alencar <[email protected]> > > --- > > I made a few comments, but nothing critical, so... > > Reviewed-by: David Lechner <[email protected]> > > I didn't find anything to add, so should be good with a v8 covering the stuff David pointed out. FWIW sashiko is clean though it does raise a missing null check if anyone forces a bind that might be good to fix. As to the DMA cache line issues, I'd ignore those. If they are a real problem with any controller (or more likely the interconnect / caches in front of it) than I think it is up to the controller driver to bounce the data. J J
