On Tue, Aug 18, 2026 at 09:20:24PM +0000, Priyank Rathod wrote:
> Per PCIe Base Specification r6.0, sec 8.4.4 ("Lane Margining at
> Receiver"), PCIe devices operating at 16.0 GT/s (Gen 4) or higher data
> rates support the Lane Margining at Receiver Extended Capability
> (ID 0x27), and it is mandatory for receivers operating at 64.0 GT/s
> (Gen 6) or higher data rates. Lane Margining allows software to
> evaluate high-speed link margins by measuring timing and voltage steps
> for each individual physical lane and receiver.Aug 18 13:57 Priyank Rathod [PATCH] PCI/pcie: Add PCIe Lane ... Aug 18 14:26 Priyank Rathod ├─>[PATCH v2] PCI/pcie: Add PCIe Lane ... Aug 18 15:49 Priyank Rathod ├─>[PATCH v3] PCI/pcie: Add PCIe Lane ... Aug 18 16:20 Priyank Rathod └─>[PATCH v4] PCI/pcie: Add PCIe Lane ... No need to rush: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v7.2#n361 The v7.3 merge window is open now, so this is likely v7.4 material.
