On Wed, Aug 12, 2026 at 08:12:01PM +0100, Mark Brown wrote:
> The encoding to trap mapping currently maps a FGT on OP_GCSPOPX to
> HFGITR_EL2.nGCSEPP but as per DDI0601 2026-06 this FGT controls trapping
> of GCSPUSHX and GCSPOPCX, and not the separate GCSPOPX instruction.
> Update the mapping to reflect the architecture.
That information seems to match the one in Arm ARM version M.c.
nGCSEPP, bit [59]
When FEAT_GCS is implemented:
Trap execution of any of the following AArch64 instructions at EL1 to
EL2:
• GCSPUSHX.
• GCSPOPCX.
It looks like GCSPOPX can fault if the record is not a valid entry, but
there seems to be no trap register bit for that.
Thanks!
Leo,
>
> Fixes: 863ac38984a82 ("KVM: arm64: Add missing HFGITR_EL2 FGT entries to
> nested virt")
> Signed-off-by: Mark Brown <[email protected]>
> ---
> arch/arm64/kvm/emulate-nested.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 3c82f392845d..b32742d9dd73 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -1432,7 +1432,7 @@ static const struct encoding_to_trap_config
> encoding_to_fgt[] __initconst = {
> SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1),
> SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1),
> SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0),
> - SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0),
> + SR_FGT(OP_GCSPOPCX, HFGITR, nGCSEPP, 0),
> SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0),
> SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0),
> SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0),
>
> --
> 2.47.3
>
