On Wed, Aug 19, 2026 at 02:55:23PM +0100, Leonardo Bras wrote: > On Wed, Aug 12, 2026 at 08:12:01PM +0100, Mark Brown wrote: > > The encoding to trap mapping currently maps a FGT on OP_GCSPOPX to > > HFGITR_EL2.nGCSEPP but as per DDI0601 2026-06 this FGT controls trapping > > of GCSPUSHX and GCSPOPCX, and not the separate GCSPOPX instruction. > > Update the mapping to reflect the architecture. > > That information seems to match the one in Arm ARM version M.c. > nGCSEPP, bit [59] > When FEAT_GCS is implemented: > Trap execution of any of the following AArch64 instructions at EL1 to > EL2: > • GCSPUSHX. > • GCSPOPCX. > > It looks like GCSPOPX can fault if the record is not a valid entry, but > there seems to be no trap register bit for that. > > Thanks! > Leo, > >
Ah, FWIW: Reviewed-by: Leonardo Bras <[email protected]>
