On Tue, Sep 01, 2026 at 10:47:00PM +0100, Mark Brown wrote:
> The encoding to trap mapping currently maps a FGT on OP_GCSPOPX to
> HFGITR_EL2.nGCSEPP but as per DDI0601 2026-06 this FGT controls trapping
> of GCSPUSHX and GCSPOPCX, and not the separate GCSPOPX instruction.
> Update the mapping to reflect the architecture.
>
> Fixes: 863ac38984a82 ("KVM: arm64: Add missing HFGITR_EL2 FGT entries to
> nested virt")
> Reviewed-by: Leonardo Bras <[email protected]>
> Signed-off-by: Mark Brown <[email protected]>
LGTM so:
Reviewed-by: Lorenzo Stoakes (ARM) <[email protected]>
> ---
> arch/arm64/kvm/emulate-nested.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 625604019fb3..3806ff0920fe 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -1445,7 +1445,7 @@ static const struct encoding_to_trap_config
> encoding_to_fgt[] __initconst = {
> SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1),
> SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1),
> SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0),
> - SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0),
> + SR_FGT(OP_GCSPOPCX, HFGITR, nGCSEPP, 0),
Yikes, yeah I see from the doc I referenced in 1/14 that that's the wrong
instruction ([0]).
I guess this wasn't visible before in any case because 9/14 is required to
actually enable this in practice?
> SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0),
> SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0),
> SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0),
>
> --
> 2.47.3
>
>
[0]:
https://support.arm.com/documentation/111107/2026-06/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register
--
Cheers, Lorenzo
