On Tue, Sep 01, 2026 at 10:46:59PM +0100, Mark Brown wrote:
> The initial EL2 setup for GCS did not include disabling of EL1 usage of
> GCS instructions, also disable these traps.
>
> Fixes: ff5181d8a2a8 ("arm64/gcs: Provide basic EL2 setup to allow GCS usage
> at EL0 and EL1")
> Reviewed-by: Leonardo Bras <[email protected]>
> Signed-off-by: Mark Brown <[email protected]>
> ---
> arch/arm64/include/asm/el2_setup.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/include/asm/el2_setup.h
> b/arch/arm64/include/asm/el2_setup.h
> index aa8ec9df8024..d308c6e6757d 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -393,6 +393,11 @@
> orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK
> orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK
>
> + /* Disable traps of GCS instructions at EL1 */
> + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK
> + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK
> + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK
(Forgive me being verbose here I'm thinking my way through things :)
So this is effectively:
Set bits from these masks:
HFGITR_EL2_nGCSEPP_MASK |
HFGITR_EL2_nGCSSTR_EL1_MASK |
HFGITR_EL2_nGCSPUSHM_EL1_MASK
Then (later instruction):
msr_s SYS_HFGITR_EL2, x2
I.e. set the hypervisor fine-grained instruction register ([0]).
And I can see from that document that for each bit:
0b1
Execution of the specified instructions is not trapped by this mechanism.
So this correctly disables these instructions:
GCSPUSHX
GCSPOPCX
GCSSTR
GCSSTTR when PSTATE.UAO is 1
GCSSTTR when the Effective value of HCR_EL2.{NV, NV1} is {1, 1}
GCSPUSHM
And these are the only listed GCS sets of instructions there.
On that basis LGTM :)
So:
Reviewed-by: Lorenzo Stoakes (ARM) <[email protected]>
[0]:
https://support.arm.com/documentation/111107/2026-06/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register
> +
> .Lskip_gce_fgt_\@:
>
> .Lset_fgt_\@:
>
> --
> 2.47.3
>
>
--
Cheers, Lorenzo
