The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple subsystems:
The JHB100 SoC is divided into multiple subsystems, and basically each subsystem includes a CRG(Clock and Reset Generator): - sys0crg/sys1crg/sys2crg/ - per0crg/per1crg/per2crg/per3crg/ - voutcrg - vcecrg - gpu0crg/gpu1crg - cpucrg - usbcrg - host0crg/host1crg - pcierpcrg - husb0crg/husb1crg - husbcmncrg - husbd0crg/husbd1crg - npucrg In the current series, we will only add the following CRG: - sys0crg/sys1crg/sys2crg/ - per0crg/per1crg/per2crg/per3crg/ The remaining CRG will be implemented in future series. This series depends on the series: https://lore.kernel.org/all/[email protected]/ and it has been tested on the StarFive JHB100 EVB-1. changes since v4: - Remove patches 1/2/3/4 in v4, and patches 1/2/3 are newly introduced in v5. - Refactor the shared clock and reset implementation into JH71x0-specific helpers, updating the affected drivers (These include patches 4/6/8/10/12/14/16/18/20/21/22 in v5.) to use the new interfaces. - Split patch 6 in v4 into patch 4 and patch 6 in the current v5. - Split patch 21 in v4 into patch 21 and patch 22 in the current v5. PATCH 17: (in v5) - Add Krzysztof's Reviewed-by tag v4: https://lore.kernel.org/all/[email protected]/ v3: https://lore.kernel.org/all/[email protected]/ v2: https://lore.kernel.org/all/[email protected]/ v1: https://lore.kernel.org/all/[email protected]/ Changhuang Liang (23): clk: starfive: jh7110-sys: Fix memory leak in reset controller register clk: starfive: JH71x0: Move reset controller registration to jh71x0 common code reset: starfive: jh7110: Match auxiliary device names to jh71x0 clk driver clk: starfive: jh71x0: Add generic CRG probe helper dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator clk: starfive: Add JHB100 System-0 clock generator driver dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator clk: starfive: Add JHB100 System-1 clock generator driver dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator clk: starfive: Add JHB100 System-2 clock generator driver dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator clk: starfive: Introduce idiv ops for inverted divider clocks clk: starfive: Expand the storage of clock parent index clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver reset: starfive: jh71x0: Support discontiguous reset IDs reset: starfive: Add StarFive JHB100 reset driver riscv: dts: starfive: jhb100: Add clocks and resets nodes .../clock/starfive,jhb100-per0crg.yaml | 70 ++ .../clock/starfive,jhb100-per1crg.yaml | 70 ++ .../clock/starfive,jhb100-per2crg.yaml | 76 +++ .../clock/starfive,jhb100-per3crg.yaml | 76 +++ .../clock/starfive,jhb100-sys0crg.yaml | 63 ++ .../clock/starfive,jhb100-sys1crg.yaml | 71 +++ .../clock/starfive,jhb100-sys2crg.yaml | 64 ++ MAINTAINERS | 13 + arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 +++++- drivers/clk/starfive/Kconfig | 72 ++- drivers/clk/starfive/Makefile | 8 + .../clk/starfive/clk-starfive-jh7110-aon.c | 2 +- .../clk/starfive/clk-starfive-jh7110-isp.c | 2 +- .../clk/starfive/clk-starfive-jh7110-stg.c | 2 +- .../clk/starfive/clk-starfive-jh7110-sys.c | 57 +- .../clk/starfive/clk-starfive-jh7110-vout.c | 2 +- drivers/clk/starfive/clk-starfive-jh7110.h | 4 - drivers/clk/starfive/clk-starfive-jh71x0.c | 161 ++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 24 +- .../clk/starfive/clk-starfive-jhb100-per0.c | 599 ++++++++++++++++++ .../clk/starfive/clk-starfive-jhb100-per1.c | 149 +++++ .../clk/starfive/clk-starfive-jhb100-per2.c | 174 +++++ .../clk/starfive/clk-starfive-jhb100-per3.c | 132 ++++ .../clk/starfive/clk-starfive-jhb100-sys0.c | 150 +++++ .../clk/starfive/clk-starfive-jhb100-sys1.c | 105 +++ .../clk/starfive/clk-starfive-jhb100-sys2.c | 129 ++++ drivers/reset/starfive/Kconfig | 9 + drivers/reset/starfive/Makefile | 1 + .../reset/starfive/reset-starfive-jh7110.c | 10 +- .../reset/starfive/reset-starfive-jh71x0.c | 99 ++- .../reset/starfive/reset-starfive-jh71x0.h | 19 + .../reset/starfive/reset-starfive-jhb100.c | 302 +++++++++ .../dt-bindings/clock/starfive,jhb100-crg.h | 542 ++++++++++++++++ .../dt-bindings/reset/starfive,jhb100-crg.h | 186 ++++++ 34 files changed, 3553 insertions(+), 88 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per0.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h -- 2.25.1
