Hi Conor, On Wed, Sep 30, 2026 at 11:43:22PM +0100, Conor Dooley wrote: > FYI clock folks, > > On Wed, Sep 30, 2026 at 05:42:54AM -0700, Changhuang Liang wrote: > > The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple > > subsystems: > > > > The JHB100 SoC is divided into multiple subsystems, and basically > > each subsystem includes a CRG(Clock and Reset Generator): > > - sys0crg/sys1crg/sys2crg/ > > - per0crg/per1crg/per2crg/per3crg/ > > - voutcrg > > - vcecrg > > - gpu0crg/gpu1crg > > - cpucrg > > - usbcrg > > - host0crg/host1crg > > - pcierpcrg > > - husb0crg/husb1crg > > - husbcmncrg > > - husbd0crg/husbd1crg > > - npucrg > > > > In the current series, we will only add the following CRG: > > - sys0crg/sys1crg/sys2crg/ > > - per0crg/per1crg/per2crg/per3crg/ > > > > The remaining CRG will be implemented in future series. > > > > This series depends on the series: > > https://lore.kernel.org/all/[email protected]/ > > and it has been tested on the StarFive JHB100 EVB-1. > > If this revision of the series is acceptable, I'd (although I'm not a > listed driver maintainer) like to send you a PR as I've done in the past > for Starfive stuff so that I can get some of these binding patches that > contain headers as part of a shared tag to be able to unblock a bunch of > the soc tree stuff. With conferences next week I understand that, with it > being -rc5, it's probably this doesn't make v7.4 but I figured it was > worth getting my intentions out there!
I am going through this series now, and I have a few minor changes to the clk drivers themselves. Feel free to send a pull for the bindings and headers though. Brian
