Document the Glymur OOBMSS PAS node with its secure GLink edge, shared-memory signaling, firmware carveouts, and power resources.
Signed-off-by: Anvesh Jain P <[email protected]> --- .../bindings/remoteproc/qcom,glymur-oob-pas.yaml | 156 +++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml new file mode 100644 index 000000000000..bd4f397da40f --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glymur-oob-pas.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,glymur-oob-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) PAS + +maintainers: + - Anvesh Jain P <[email protected]> + +description: | + Qualcomm Glymur Out-of-Band Management Subsystem (OOBMSS) contains two + processors running Zephyr, managed together as one remoteproc instance. + The Out-of-Band Trusted Execution Environment (OOB-TEE) is the primary + processor. The OOB-Non-Secure processor is an auxiliary processor that + depends on the primary processor and cannot function independently. + + The primary processor runs the primary image, while the auxiliary + processor runs the secondary image. Each processor has its own DTB. + The two images and their DTBs have separate PAS identifiers for + authentication and dedicated reserved-memory carveouts. + + OOBMSS is booted by earlier-stage firmware and uses an XO clock and the + CX and MX power domains. Shared Memory Point-to-Point (SMP2P) provides + boot, shutdown, handover and ping/pong signaling, as well as fatal error + notifications. The subsystem exposes a secure GLink edge to the host, + with doorbell interrupts provided by the Inter-Processor Communication + Controller (IPCC). + +properties: + compatible: + enum: + - qcom,glymur-oobmss-pas + + reg: + maxItems: 1 + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Pong interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: pong + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + power-domains: + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + items: + - const: cx + - const: mx + + memory-region: + items: + - description: Secure firmware carveout + - description: Secure device tree carveout + - description: Non-secure firmware carveout + - description: Non-secure device tree carveout + + firmware-name: + items: + - description: Secure firmware + - description: Secure device tree firmware + - description: Non-secure firmware + - description: Non-secure device tree firmware + + qcom,smem-states: + minItems: 2 + description: States used by the AP to signal OOBMSS + + qcom,smem-state-names: + minItems: 2 + description: The names of the state bits used for SMP2P output + +required: + - compatible + - reg + - power-domains + - power-domain-names + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #define IPCC_MPROC_OOB_S 56 + #define IPCC_MPROC_OOB 55 + + remoteproc@1f000000 { + compatible = "qcom,glymur-oobmss-pas"; + reg = <0x1f000000 0x30000>; + + interrupts-extended = <&intc GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, + <&smp2p_oobmss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_oobmss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_oobmss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_oobmss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_oobmss_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "pong"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&oob_secure_mem>, <&oobdtbqc_mem>, + <&oob_nonsecure_mem>, <&oobdtboem_mem>; + firmware-name = "qcom/glymur/oobmss_tee.mbn", + "qcom/glymur/oobmss_qc_dtb.mbn", + "qcom/glymur/oobmss_ns.mbn", + "qcom/glymur/oobmss_oem_dtb.mbn"; + qcom,smem-states = <&smp2p_oobmss_out 1>, + <&smp2p_oobmss_out 8>; + qcom,smem-state-names = "stop", "ping"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_OOB_S + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_OOB_S IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "oobmss"; + qcom,remote-pid = <20>; + }; + + }; -- 2.34.1
