On Mon, Apr 29, 2013 at 10:49 AM, Kees Cook <keesc...@chromium.org> wrote:
> On Fri, Apr 26, 2013 at 3:14 PM, H. Peter Anvin <h...@zytor.com> wrote:
>> On 04/26/2013 02:47 PM, H. Peter Anvin wrote:
>>> On 04/26/2013 12:03 PM, Kees Cook wrote:
>>>> +
>>>> +static inline void cpuid(u32 id, u32 *a, u32 *b, u32 *c, u32 *d)
>>>> +{
>>>> + /* Handle x86_32 PIC using ebx. */
>>>> + asm volatile("movl %%ebx, %%edi \n\t"
>>>> + "cpuid \n\t"
>>>> + "xchgl %%edi, %%ebx\n\t"
>>>> + : "=a" (*a),
>>>> + "=D" (*b),
>>>> + "=c" (*c),
>>>> + "=d" (*d)
>>>> + : "a" (id)
>>>> + );
>>>> +}
>>>
>>> Please don't constrain registers unnecessarily.
>>>
>>> You can use "=r" there and let gcc assign whatever free register it pleases.
>>>
>>> You can also limit that to only:
>>>
>>> #if defined(__i386__) && defined(__PIC__)
>>>
>>
>> How is this for a "beauty":
>>
>>
>> #if defined(__i386__) && defined (__PIC__)
>> # define EBX_REG "=r"
>> #else
>> # define EBX_REG "=b"
>> #endif
>>
>> asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif ; "
>> "cpuid ; "
>> ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif"
>> : "=a" (*a), "=c" (*c), "=d" (*d),
>> EBX_REG (*b)
>> : "a" (leaf), "c" (subleaf));
>>
>
> Oh, very nice on the ifnc and register define! Is the leaf/subleaf
> stuff needed there? That piece doesn't make sense to me.
Ah, nevermind, I just need the "leaf" bit for the cpuid input. Thanks!
-Kees
--
Kees Cook
Chrome OS Security
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