On Tue, 14 May 2013, Ulf Hansson wrote: > From: Ulf Hansson <[email protected]> > > Previously the DSI PLL divider rate was initialised statically and > assumed to be 1. Before the common clock framework were enabled for > ux500, a call to clk_set_rate() would always update the HW registers > no matter what the current setting was. > > This patch makes sure the actual hw settings and the sw assumed > settings are matched. > > Signed-off-by: Ulf Hansson <[email protected]> > Signed-off-by: Paer-Olof Haakansson <[email protected]> > Cc: Lee Jones <[email protected]> > --- > drivers/mfd/db8500-prcmu.c | 2 ++ > 1 file changed, 2 insertions(+)
I understand that this is causing an issue for the Multimedia guys who use this. As it's causing an issue and you are 'the' ST-E clock guru, I'll tentatively apply this to my v3.10 -fixes branch. If anyone has any arguments against it, please step forward. -- Lee Jones Linaro ST-Ericsson Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
