On 07/18/2013 04:42 PM, Peter Zijlstra wrote: > On Thu, Jul 18, 2013 at 01:39:28PM +0800, Yan, Zheng wrote: >> On 07/18/2013 01:36 PM, Yan, Zheng wrote: >>> From: "Yan, Zheng" <[email protected]> >>> >>> Compare to old atom, Silvermont has offcore and has more events >>> that support PEBS. >>> >>> Silvermont has two offcore response configuration MSRs, but the >>> event code for OFFCORE_RSP_1 is 0x02b7. To avoid complicating >>> intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to define offcore >>> MSRs. So intel_fixup_er() can find the code for OFFCORE_RSP_1 >>> by x86_pmu.extra_regs[1].event. >>> >> >> Document is at >> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf, >> but it has no PEBS event list. > > Why isn't this in the regular SDM like all the other stuff? >
I don't know, probably they still haven't finished the document yet. (above PDF has no PEBS event list). -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
