On 27/03/14 09:19 AM, Tejun Heo wrote:
On Thu, Mar 27, 2014 at 05:57:37PM +1100, Benjamin Herrenschmidt wrote:
I've contacted Marvell, but I was wondering if anybody here had already
experienced something similar or has an idea of what else the chip
might be doing wrong so we can try to find a workaround ?
No idea. First time to hear such problem. :(
There are other Marvell controllers that do DMA requests from the wrong
PCI function ID and cause IOMMU issues, so it seems like testing on such
systems (or just validating the DMA transactions done by the controller
by some other means) isn't something that Marvell likes to do.
Presumably reading from address 0 is normally fine without an IOMMU, so
this problem wouldn't be noticed otherwise.
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