On Tue, 2014-04-08 at 21:48 +0200, Rabin Vincent wrote: [...] > For any other CPU to pull in the writable entry it would have to get a > TLB miss inside the loop in multi_cpu_stop(), after the state transition > to MULTI_STOP_RUN and before the state transition to MULTI_STOP_EXIT. > This is unlikely, but theoretically possible, for example if > multi_cpu_stop() straddles sections.
With speculative execution it is also possible for the CPU to fill the TLB with entries for a memory address that the program would never actually access. Basically, whatever is in the MMU registers and page tables at any given time, the CPU can speculatively use that address translation and read that memory. And if it's marked cacheable, pull it into the cache. Oh, and if there is a dirty cacheline in another CPU/clusters cache, move that dirty entry over into it's own cache (I believe). -- Tixy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
