On 14/05/2014 at 22:15:17 +0200, Sebastian Hesselbarth wrote :
> + /* clock divider cells */
> + parent_names[1] = avpllb_names[CH4];
> + parent_names[2] = avpllb_names[CH5];
> + parent_names[3] = avpllb_names[CH6];
> + parent_names[4] = avpllb_names[CH7];
> +
> + parent_names[0] = refclk_names[SYSPLL];
It should actually be:
parent_names[0] = avpllb_names[CH4];
parent_names[1] = avpllb_names[CH5];
parent_names[2] = avpllb_names[CH6];
parent_names[3] = avpllb_names[CH7];
parent_names[4] = refclk_names[SYSPLL];
> + data = &bg2_divs[CLKID_SYS];
> + clks[CLKID_SYS] = berlin2_div_register(&data->map, base, data->name,
> + data->div_flags, parent_names, 5, data->flags, &lock);
> +
> + parent_names[0] = refclk_names[CPUPLL];
> + parent_names[5] = refclk_names[MEMPLL];
The only valid choice here should be (remember, we are not adding 1 to
the index anymore):
parent_names[4] = refclk_names[MEMPLL];
> + data = &bg2_divs[CLKID_CPU];
> + clks[CLKID_CPU] = berlin2_div_register(&data->map, base, data->name,
> + data->div_flags, parent_names, 6, data->flags, &lock);
> +
This is where it gets tricky, now we should have:
parent_names[0] = avpllb_names[CH4];
parent_names[1] = avplla_names[CH5];
parent_names[2] = avpllb_names[CH6];
parent_names[3] = avpllb_names[CH7];
parent_names[4] = refclk_names[SYSPLL];
> + parent_names[0] = refclk_names[SYSPLL];
> + for (n = CLKID_DRMFIGO; n <= CLKID_APP; n++) {
> + data = &bg2_divs[n];
> + clks[n] = berlin2_div_register(&data->map, base, data->name,
> + data->div_flags, parent_names, 5, data->flags, &lock);
> + }
> +
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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