On Thu, Jul 17, 2014 at 3:50 AM, Borislav Petkov <b...@alien8.de> wrote:
> Well, maybe it is about time we tracked shared banks.
For cpus that support CMCI and the MCi_CTL2 registers we do track
sharing. Only one cpu gets to be the "owner" of a bank that supports
CMCI (the first one to find it and set bit 30 in the CTL2 register).
The test_bit() at the top of the loop in machine_check_poll() makes
sure only the owner of a bank actually looks at it.
for (i = 0; i < mca_cfg.banks; i++) {
if (!mce_banks[i].ctl || !test_bit(i, *b))
continue;
If we don't have CMCI, then we don't have the CTL2 registers, and
so have no way to find out which banks are shared.
> We can evaluate later if the IRQs disabling is too heavy after all.
I'd be surprised if it was a problem in practice. If we have CMCI,
then we limit the banks that we look at (and if we see a high rate
of interrupts, then we turn off interrupts an poll).
If we don't have CMCI, then we are polling at a pretty low rate
(current code adjusts the rate higher if we are finding errors to
log, but we don't let that rate rise forever ... cap is ~ 1HZ).
-Tony
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
