On Mon, Aug 25, 2014 at 10:04 PM, Gleb Natapov <g...@kernel.org> wrote:
> On Mon, Aug 25, 2014 at 11:16:34AM +0800, Dennis Chen wrote:
>> On Sun, Aug 24, 2014 at 5:38 PM, Gleb Natapov <g...@kernel.org> wrote:
>> > On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>> >> This patch is used to construct the eptp in vmx mode with values
>> >> readed from MSR according to the intel x86 software developer's
>> >> manual.
>> >>
>> >> static u64 construct_eptp(unsigned long root_hpa)
>> >> {
>> >> - u64 eptp;
>> >> + u64 eptp, pwl;
>> >> +
>> >> + if (cpu_has_vmx_ept_4levels())
>> >> + pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>> >> + else {
>> >> + WARN(1, "Unsupported page-walk length of 4.\n");
>> > Page-walk length of 4 is the only one that is supported.
>> >
>> Since there is a bit 6 in IA32_VMX_EPT_VPID_CAP MSR indicating the
>> support for the page-walk length, I think sanity check is necessary.
>> But I just checked the code, it's already done in the hardware_setup()
>> function which will disable ept feature if the page-wake length is not
>> 4. Gleb, any comments for the memory type check part?
> Looks fine, but are there CPUs out there that do not support WB for eptp?
> Since
> there was no bug reports about it I assume no.
Hmm, currently I can't find a x86 processor that don't support WB for
eptp, also there is no relevant bug reported.
I just read the intel SDM 24.6.11: SW should read the VMX capability
MSR_IA32_VMX_EPT_VPID_CAP to determine
what EPT MT are supported. But looks like this is not a big concern in
the community, so let's go back this thread if
we encounter one unfornately in the future. Thanks for the comments.
>
> --
> Gleb.
--
Den
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