On Wed, Oct 22, 2014 at 04:49:52PM +0200, Peter Zijlstra wrote:
> On Mon, Oct 13, 2014 at 04:45:40PM +0300, Alexander Shishkin wrote:
> > +static void pt_config_start(bool start)
> > +{
> > + u64 ctl;
> > +
> > + rdmsrl(MSR_IA32_RTIT_CTL, ctl);
> > + if (start)
> > + ctl |= RTIT_CTL_TRACEEN;
> > + else
> > + ctl &= ~RTIT_CTL_TRACEEN;
> > + wrmsrl(MSR_IA32_RTIT_CTL, ctl);
> > +
> > + /*
> > + * A wrmsr that disables trace generation serializes other PT
> > + * registers and causes all data packets to be written to memory,
> > + * but a fence is required for the data to become globally visible.
> > + *
> > + * The below WMB, separating data store and aux_head store matches
> > + * the consumer's RMB that separates aux_head load and data load.
> > + */
> > + if (!start)
> > + wmb();
> > +}
>
> wmb is sfence, is that sufficient? One would have expected an mfence
> since that would also orders later reads.
Silly me, we're separating two stores here. Ignore that.
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