The PREFETCHW workaround for llock/scond livelock was not sufficient after
all and we had to do some work there. Extending testing of quad core FPGA
builds shows things pretty stable, whereas w/o patches some of the LTP tests
(shm_open/23-1) would cause the system to go bonkers.
Changes since v1* (all thx to Peter Zijlstra)
* 3/6 - updated changelog
* 4/6 - updated changelog
arch_write_unlock() need not use LLOCK/SCOND
* 5/6 - Conditional implementation of SCOND_FAIL_RETRY* in atomics (reduced dup)
Handle overflow of delay counter in SCOND_FAIL_RETRY_ASM
* 6/6 - updated changelog
[*]
http://lkml.kernel.org/r/1438596188-10875-1-git-send-email-vgu...@synopsys.com
Vineet Gupta (6):
Revert "ARCv2: STAR 9000837815 workaround hardware exclusive
transactions livelock"
ARC: refactor atomic inline asm operands with symbolic names
ARC: LLOCK/SCOND based spin_lock
ARC: LLOCK/SCOND based rwlock
ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with
exponential backoff
ARCv2: spinlock/rwlock: Reset retry delay when starting a new
spin-wait cycle
arch/arc/Kconfig | 5 +
arch/arc/include/asm/atomic.h | 79 +++--
arch/arc/include/asm/spinlock.h | 539 +++++++++++++++++++++++++++++++++-
arch/arc/include/asm/spinlock_types.h | 2 +
arch/arc/kernel/setup.c | 4 +
5 files changed, 591 insertions(+), 38 deletions(-)
--
1.9.1
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