Commit-ID:  2a853e1123cbbb43ff74cc47b4ec582ce34df262
Gitweb:     http://git.kernel.org/tip/2a853e1123cbbb43ff74cc47b4ec582ce34df262
Author:     Liang, Kan <[email protected]>
AuthorDate: Fri, 3 Jul 2015 20:08:27 +0000
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 4 Aug 2015 10:17:00 +0200

perf/x86/intel/pebs: Fix event disable PEBS buffer drain

When disabling a PEBS event, we need to drain the buffer. Doing so
requires a correct cpuc->pebs_active mask.

The current code clears the pebs_active bit before draining the
buffer. Fix that.

Signed-off-by: "Liang, Kan" <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver<[email protected]>
Link: 
http://lkml.kernel.org/r/37d7c6cf3e00a74b8858931c1db2f07701885...@shsmsx103.ccr.corp.intel.com
[ Fixed the SOB. ]
Signed-off-by: Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel_ds.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c 
b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 2f7ee05..8e564f8 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -789,6 +789,11 @@ void intel_pmu_pebs_disable(struct perf_event *event)
        struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
        struct debug_store *ds = cpuc->ds;
+       bool large_pebs = ds->pebs_interrupt_threshold >
+               ds->pebs_buffer_base + x86_pmu.pebs_record_size;
+
+       if (large_pebs)
+               intel_pmu_drain_pebs_buffer();
 
        cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 
@@ -797,12 +802,8 @@ void intel_pmu_pebs_disable(struct perf_event *event)
        else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
                cpuc->pebs_enabled &= ~(1ULL << 63);
 
-       if (ds->pebs_interrupt_threshold >
-           ds->pebs_buffer_base + x86_pmu.pebs_record_size) {
-               intel_pmu_drain_pebs_buffer();
-               if (!pebs_is_enabled(cpuc))
-                       perf_sched_cb_dec(event->ctx->pmu);
-       }
+       if (large_pebs && !pebs_is_enabled(cpuc))
+               perf_sched_cb_dec(event->ctx->pmu);
 
        if (cpuc->enabled)
                wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
--
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