> From: linux-arm-kernel > [mailto:linux-arm-kernel-boun...@lists.infradead.org] On Behalf Of Mark > Brown > Sent: Thursday, October 1, 2015 2:18 AM > To: yitian <yitian...@tangramtek.com> > Cc: alsa-de...@alsa-project.org; w...@the-dreams.de; > linux-kernel@vger.kernel.org; andrew.jack...@arm.com; ti...@suse.com; > lgirdw...@gmail.com; pe...@perex.cz; > linux-arm-ker...@lists.infradead.org > Subject: Re: [RESEND PATCH 1/1] ASoC: dwc: correct irq clear method > > On Tue, Sep 29, 2015 at 10:39:00PM +0800, yitian wrote: > > from Designware I2S datasheet, irq is cleared by reading from > > TOR/ROR registers, rather than by writing into them. > > This doesn't apply against current code, please check and resend. Hi Mark:
Thanks for your comments. Maybe I misunderstand your meaning. Please correct me. I synced up to latest kernel branch, the code is the same as what this patch was generated. I checked designware I2S spec "version 1.08a June 2014", it specified that the TOR and ROR registers are read only and reading the last bit will clear tx/rx overrun irq. Also I have checked this register by writing its last bit, the overrun irq is not cleared. But if I read the last bit, the overrun irq is cleared. That means the spec is correct. Can you please let me know what else I should double check? Thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
