Hello everyone,
I was looking at my local diffs to our 2.6.10 tree in order to clean stuff up for commit of the Gayle PCMCIA code. Upon doing this I came across the following (again, already noticed this back in 2000): I have a scanned version of a preliminary specification for Gayle which shows the following info for the IDE part of Gayle on the A600/A1200: ------------------- 7.0 IDE HARD DRIVE The IDE (AT) hard drive requires two mutually exclusive chip selects. Please see the chart below for address range in which each is active. The _IOW and _IOR signals have timing that is valid for IDE hard drives during these cycles. Data register accesses can be performed faster than control register accesses. Accesses to the control registers are called "8 bit accesses" while those to the data register are called "16 bit accesses". Shown below is a table that gives the chip select and access speed versus address range. A4 A3 A2 Address Range Chip Select Speed 0 0 0 $0DA0000 to $0DA0FFF _CS1 8 bit 0 0 1 $0DA1000 to $0DA1FFF _CS2 8 bit 0 1 0 $0DA2000 to $0DA2FFF _CS1 16 bit 0 1 1 $0DA3000 to $0DA3FFF _CS2 16 bit 1 0 X $0DA4000 to $0DA5FFF None 8 bit 1 1 X $0DA6000 to $0DA7FFF None 16 bit 7.3 IDE Register Map The disk drive address lines DA0, DA1, and DA2 are expected to be connected to processor address lines A2, A3, and A4 respectively. When connected in this fashion, the following memory map results: Addr on A1000+ Addr on AT Valid Data Read Function Write Function $0DA1018 3F6 8 bits Alternate Status Device Control $0DA101C 3F7 8 bits Drive address Not used $0DA0004 1F1 8 bits Error Register Features $0DA0008 1F2 8 bits Sector Count Sector Count $0DA000C 1F3 8 bits Sector Number Sector Number $0DA0010 1F4 8 bits Cylinder Low Cylinder Low $0DA0014 1F5 8 bits Cylinder High Cylinder High $0DA0018 1F6 8 bits Drive/Head Drive/Head $0DA001C 1F7 8 bits Status Command $0DA2000 1F0 16 bits Data Data ------------------- Which means that with the current definitions in the driver, the data is read using 8 bit cycles... It also nicely shows how IDE doublers work: they just use _CS2 to select the second controller... I changed the definitions to conform to the above table, and did some simple timings using hdparm -t: Old driver: 1.16 MB/s New driver: 1.59 MB/s So it does make a difference... Any problems with converting to the above addresses, and can anyone test it on an A4000 (it has different addresses, but I'm assuming the 8/16 bit thing holds there too)? Kind regards, Kars. - To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
