On Thu, 24 Feb 2005, Kars de Jong wrote:
> 7.0 IDE HARD DRIVE
>
> The IDE (AT) hard drive requires two mutually exclusive chip selects. Please
> see the chart
> below for address range in which each is active. The _IOW and _IOR signals
> have timing that is
> valid for IDE hard drives during these cycles.
> Data register accesses can be performed faster than control register
> accesses. Accesses to the
> control registers are called "8 bit accesses" while those to the data
> register are called "16 bit
> accesses". Shown below is a table that gives the chip select and access speed
> versus address
> range.
>
> A4 A3 A2 Address Range Chip Select Speed
> 0 0 0 $0DA0000 to $0DA0FFF _CS1 8 bit
> 0 0 1 $0DA1000 to $0DA1FFF _CS2 8 bit
> 0 1 0 $0DA2000 to $0DA2FFF _CS1 16 bit
> 0 1 1 $0DA3000 to $0DA3FFF _CS2 16 bit
> 1 0 X $0DA4000 to $0DA5FFF None 8 bit
> 1 1 X $0DA6000 to $0DA7FFF None 16 bit
>
> 7.3 IDE Register Map
>
> The disk drive address lines DA0, DA1, and DA2 are expected to be connected
> to processor
> address lines A2, A3, and A4 respectively. When connected in this fashion,
> the following
> memory map results:
>
> Addr on A1000+ Addr on AT Valid Data Read Function Write Function
> $0DA1018 3F6 8 bits Alternate Status Device Control
> $0DA101C 3F7 8 bits Drive address Not used
> $0DA0004 1F1 8 bits Error Register Features
> $0DA0008 1F2 8 bits Sector Count Sector Count
> $0DA000C 1F3 8 bits Sector Number Sector Number
> $0DA0010 1F4 8 bits Cylinder Low Cylinder Low
> $0DA0014 1F5 8 bits Cylinder High Cylinder High
> $0DA0018 1F6 8 bits Drive/Head Drive/Head
> $0DA001C 1F7 8 bits Status Command
> $0DA2000 1F0 16 bits Data Data
>
> -------------------
>
> Which means that with the current definitions in the driver, the data is
> read using 8 bit cycles...
>
> It also nicely shows how IDE doublers work: they just use _CS2 to select
> the second controller...
Yep, they sacrifice the not-really-needed `1018' and unused `101c' registers to
support a second port. Should work on PC as well.
> I changed the definitions to conform to the above table, and did some
So you changed GAYLE_DATA from 0x00 to 0x2000?
> simple timings using hdparm -t:
>
> Old driver: 1.16 MB/s
> New driver: 1.59 MB/s
>
> So it does make a difference...
Impressive!
> Any problems with converting to the above addresses, and can anyone test
> it on an A4000 (it has different addresses, but I'm assuming the 8/16
> bit thing holds there too)?
I'm afraid it won't work, but I (or someone else, my Amiga is still not set up
since my last move) could give it a try anyway, you wouldn't loose data if it
doesn't work.
The A4000 Gayle is a lot different from the A600/A1200. E.g. the interrupt
register is at offset 0x1000, compared to the data register.
And when I wrote support for the Amiga 4000 IDE interface back in 1994, I did
reverse engineer the A4000's scsi.device, so I think I would have noticed if
they used offset 0x2000 for the data register.
Perhaps we can ask Dave Haynie? Is he still around?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [EMAIL PROTECTED]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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