Hi Adrian, On Wed, Jun 12, 2019 at 09:42:27AM +0300, Adrian Hunter wrote: > On 12/05/19 10:41 PM, Angelo Dureghello wrote: > > Some controller as the ColdFire eshdc may require an endianness > > byte swap, becouse DMA read endianness is not configurable. > > becouse -> because > ok
> Do any other drivers have this issue? > host/mxcmmc.c for PPC devices is doing a similar swap (buffer_swap32). > > > > Signed-off-by: Angelo Dureghello <[email protected]> > > --- > > drivers/mmc/host/sdhci.c | 19 +++++++++++++++++++ > > drivers/mmc/host/sdhci.h | 7 +++++++ > > 2 files changed, 26 insertions(+) > > > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > > index 97158344b862..317dcfb4bb4c 100644 > > --- a/drivers/mmc/host/sdhci.c > > +++ b/drivers/mmc/host/sdhci.c > > @@ -2592,6 +2592,18 @@ static const struct mmc_host_ops sdhci_ops = { > > .card_busy = sdhci_card_busy, > > }; > > > > +static void sdhci_be_to_le(char *buff, u32 length) > > +{ > > + int i, size = length >> 2; > > + u32 *buffer = (u32 *)buff; > > + u32 temp; > > + > > + for (i = 0; i < size; i++) { > > + temp = *buffer; > > + *buffer++ = __le32_to_cpu(temp); > > + } > > +} > > + > > > > /*****************************************************************************\ > > * > > * > > * Request done > > * > > @@ -2647,6 +2659,13 @@ static bool sdhci_request_done(struct sdhci_host > > *host) > > host->bounce_addr, > > host->bounce_buffer_size, > > DMA_FROM_DEVICE); > > + > > + if (host->quirks2 & > > + SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP) > > + sdhci_be_to_le( > > + host->bounce_buffer, > > + length); > > How come it only affects the bounce buffer? What about if there is no > bounce buffer? > Right, Will check where how to apply the swap also without bounce buffer. > > + > > sg_copy_from_buffer(data->sg, > > data->sg_len, > > host->bounce_buffer, > > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > > index d6bcc584c92b..38fa69678cec 100644 > > --- a/drivers/mmc/host/sdhci.h > > +++ b/drivers/mmc/host/sdhci.h > > @@ -486,6 +486,13 @@ struct sdhci_host { > > */ > > #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) > > > > +/* > > + * On some architectures, as ColdFire/m68k, native endianness is big > > endian, > > + * and the dma buffer is filled in big endian order only (no other > > options). > > + * So, a swap is needed for these specific cases. > > + */ > > +#define SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP (1<<19) > > + > > int irq; /* Device IRQ */ > > void __iomem *ioaddr; /* Mapped address */ > > char *bounce_buffer; /* For packing SDMA reads/writes */ > > > Regards, Angelo
