enable controller caps to support h/w clock gating
Signed-off-by: Philip Rakity <[email protected]>
---
drivers/mmc/host/sdhci-pxa.c | 18 +++++++++++++++++-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c
index 2a6b156..b31d3d5 100644
--- a/drivers/mmc/host/sdhci-pxa.c
+++ b/drivers/mmc/host/sdhci-pxa.c
@@ -138,10 +138,23 @@ static void platform_reset_exit(struct sdhci_host *host,
u8 mask)
}
}
+#ifdef CONFIG_MMC_CLKGATE
+static void platform_hw_clk_gate(struct sdhci_host *host)
+{
+ int enable;
+
+ enable = host->mmc->clk_gated;
+ programFIFO(host, enable);
+}
+#endif
+
static struct sdhci_ops sdhci_pxa_ops = {
.get_f_max_clock = NULL,
.set_signaling_voltage = set_signaling_voltage,
.platform_reset_exit = platform_reset_exit,
+#ifdef CONFIG_MMC_CLKGATE
+ .platform_hw_clk_gate = platform_hw_clk_gate,
+#endif
};
/*****************************************************************************\
@@ -209,8 +222,11 @@ static int __devinit sdhci_pxa_probe(struct
platform_device *pdev)
host->irq = irq;
host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
- /* enable mmc bus width testing */
+#ifdef CONFIG_MMC_CLKGATE
+ host->mmc->caps |= MMC_CAP_HW_CLOCK_GATING | MMC_CAP_BUS_WIDTH_TEST;
+#else
host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
+#endif
/* If slot design supports 8 bit data, indicate this to MMC. */
if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
--
1.7.0.4
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