On Fri, Oct 12, 2012 at 4:02 PM, Ulf Hansson <[email protected]> wrote:
> From: Ulf Hansson <[email protected]> > > For the ux500v2 variant non power of two block sizes are supported. > This will make it possible to decrease data overhead for SDIO > transfers. Although we need to put some constraints to the alignment > of the buffers when enabling this feature. > > Buffers must be 4 bytes aligned due to restrictions that the PL18x > FIFO accesses must be done in a 4 byte aligned manner. Moreover we > need to enable DMA_REQCTL for SDIO to support write of non 32 bytes > aligned sg element lengths. In PIO mode any buffer length can be > handled as long as the buffer address is 4 byte aligned. > > Signed-off-by: Ulf Hansson <[email protected]> > Signed-off-by: Per Forlin <[email protected]> Reviewed-by: Linus Walleij <[email protected]> I finally understand how this works now. Bonus for comments like this: > +/* > + * DMA request control is required for write > + * if transfer size is not 32 byte aligned. > + * DMA request control is also needed if the total > + * transfer size is 32 byte aligned but any of the > + * sg element lengths are not aligned with 32 byte. > + */ > #define MCI_ST_DPSM_DMAREQCTL (1 << 12) Which make you understand what is actually happening. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
