2012/10/12 Ulf Hansson <[email protected]>: > From: Ulf Hansson <[email protected]> > > For the ux500v2 variant non power of two block sizes are supported. > This will make it possible to decrease data overhead for SDIO > transfers. Although we need to put some constraints to the alignment > of the buffers when enabling this feature. > > Buffers must be 4 bytes aligned due to restrictions that the PL18x > FIFO accesses must be done in a 4 byte aligned manner. Moreover we > need to enable DMA_REQCTL for SDIO to support write of non 32 bytes > aligned sg element lengths. In PIO mode any buffer length can be > handled as long as the buffer address is 4 byte aligned. > > Signed-off-by: Ulf Hansson <[email protected]> > Signed-off-by: Per Forlin <[email protected]>
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