On Wednesday 12 June 2013, [email protected] wrote:
> +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> +{
> + struct dw_mci_socfpga_priv_data *priv = host->priv;
> +
> + clk_disable_unprepare(host->ciu_clk);
> + regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> + priv->hs_timing);
> + clk_prepare_enable(host->ciu_clk);
> +
> + host->bus_hz /= (priv->ciu_div + 1);
> + return 0;
> +}
Sorry for being so late in the game here, but why do you need a
regmap_write() call in the driver here? Shouldn't you just be able
to use the clk_set_rate() interface from the generic dw_mmc-pltfm
code?
Arnd
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