Hi! Brandon Thanks alot! for valuable input.......
i am now using flush_cache_all(); for making all memories updated for testing. and it is working :) with regards Somz On Sat, Jun 14, 2008 at 5:02 AM, Azbell, Brandon <[EMAIL PROTECTED]> wrote: > Somz, > > The parameter set looks fine and as you indicated, works fine > for the 1024 byte transfer. > > Regarding the 64-byte transfer, which was not represented in the > parameters you provided, I suspect that it is getting stuck in the L1 > Cache, or possibly L2 Cache, but not actually getting to system memory > (DDR). For the 1024 byte transfer, the cache controllers may be needing > to flush to make room and therefore it "appears" to be working. > > Do you perform a cache flush on the SRC buffer prior to > triggering the DMA? > Also, do you perform a cache invalidate on the DST buffer prior > to reading the buffer and verifying the contents? > > You should perform this in order to ensure the new contents of > the SRC buffer make it to system memory (DDR) prior to the DMA transfer. > > Brandon Azbell > > -- "Like it or not, you're in the Software Business" -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
