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Op 21 jun 2008, om 19:05 heeft Paul Walmsley het volgende geschreven:
On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit. This is a departure from previous silicon,
which only had an initiator standby bit.
This means we need to test the target idle bit after enabling
dss1_alwon_fclk. Previous clock code has done the wrong thing since
ES2
came out: it's either tested the wrong bit, causing intermittent
Clock dss1_alwon_fck didn't enable in 100000 tries
messages; or not tested anything at all, causing intermittent crashes
during DISPC initialization with:
Unhandled fault: external abort on non-linefetch (0x1028)
This patch modifies omap2_clk_wait_ready() to wait for the DSS to
become
accessible after dss1_alwon_fclk is enabled.
Thanks to Anand Gadiyar <[EMAIL PROTECTED]> for identifying one of the
problem patches.
What this patch and the timer suppression patch I now get:
PowerTOP version 1.10 (C) 2007 Intel Corporation
Cn Avg residency P-states (frequencies)
C0 (cpu running) ( 0.0%)
C0 0.0ms ( 0.0%)
C1 188.9ms (0.7%)*
C2 2036.1ms (8.0%)*
C3 23285.1ms (91.3%)*
Wakeups-from-idle per second : 61.7 interval: 3.0s
Top causes for wakeups:
44.9% ( 57.7) <interrupt> : musb_hdrc.0
17.9% ( 23.0) <interrupt> : gp timer
14.3% ( 18.3) USB device 2-1.2 : LCD2USB Interface (Till Harbaum)
9.9% ( 12.7) lcd4linux : do_nanosleep (hrtimer_wakeup)
7.5% ( 9.7) USB device 2-1.4 : Linksys USB2.0 Network Adapter
(USB)
3.9% ( 5.0) Xfbdev : fbcon_add_cursor_timer
(cursor_timer_handler)
0.5% ( 0.7) hald : schedule_timeout (process_timeout)
0.3% ( 0.3) dropbear : sk_reset_timer (tcp_write_timer)
0.3% ( 0.3) <kernel core> : neigh_table_init_no_netlink
(neigh_periodic_timer)
0.3% ( 0.3) pulseaudio : schedule_timeout (process_timeout)
0.3% ( 0.3) init : schedule_timeout (process_timeout)
The dispc crashes are gone and I get fewer wakeups per second :)
regards,
Koen
* There's a bug in powertop 1.10 that reports percentages wrong, so
the percentages where approximated by hand.
C0 (cpu running) ( 0.0%)
C0 0.0ms ( 0.0%)
C1 176.5ms ( 4.7%)
C2 3601.7ms (4090.7%)
C3 17956.3ms (92938.0%)
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