Hello Peter,
On Fri, 18 Jul 2008, Peter 'p2' De Schrijver wrote:
> On Thu, Jul 17, 2008 at 07:34:52PM -0600, ext Paul Walmsley wrote:
> > TWL4030 interrupt status register bits can be cleared in one of two ways:
> > either by reading from the register, or by writing a 1 to the
> > appropriate bit(s) in the register. This behavior can be altered at any
> > time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read").
> >
> > twl4030-core.c does not touch these *_SIH_CTRL registers during boot,
> > and the TWL4030 TRM is deeply confused as to whether COR=1 means that
> > the registers are cleared on reads, or cleared on writes.
> >
>
> That's true. But reality is fortunately not so confused :) COR=1 means
> all IRQs are acknowledged when reading the corresponding ISR. COR=0
> means you need to write 1 to the bits in the ISR for interrupts you want to
> acknowledge.
>
> Hope this helps,
thanks very much, it does help. Ought to save a little time on boot.
Will post an updated set tomorrow...
- Paul
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