Filling the set_rate and round_rate fields of dpll4_m4_ck makes
this clock programmable through clk_set_rate(). This is needed
to give omapfb control over the dss1_alwon_fck rate.
Signed-off-by: Mans Rullgard <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/clock34xx.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 4adf78e..e51e182 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -875,6 +875,8 @@ static struct clk dpll4_m6_ck = {
PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
--
1.6.0.2
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