"ext Tomi Valkeinen" <[EMAIL PROTECTED]> writes:
> Hi,
>
> On Mon, 2008-12-08 at 02:24 -0700, ext Paul Walmsley wrote:
>> Hi Tomi,
>>
>> On Mon, 8 Dec 2008, Tomi Valkeinen wrote:
>>
>> > On Sat, 2008-12-06 at 16:51 -0700, ext Paul Walmsley wrote:
>> > > Hi Tomi,
>> > >
>> > > nice test case.
>> > >
>> > > On Fri, 5 Dec 2008, [EMAIL PROTECTED] wrote:
>> > >
>> > > > I have had strange clk_enable() crashes with DSS2, and now I managed to
>> > > > isolate it. With the included patch, on OMAP3 SDP board, with default
>> > > > kernel config, I always get the crash below. In this example case it
>> > > > happens at specific time on boot, but with DSS2 it happens randomly at
>> > > > runtime, when I enable the DSS clocks.
>> > >
>>
>> At this point my guess would be that it is a DSS driver problem, but I
>> don't think it is clear yet.
>>
>
> I don't know much about power and clock domains, but I believe I found
> the reason and fix for this. At least this should point to the right
> direction.
>
> It looks to me that when I do clk_enable() to a clock which is inside a
> turned off powerdomain, clk_enable() function will return before the
> powerdomain is fully turned on. Reading PM_PWSTST_DSS shows that the
> powerdomain is still in transition state.
I debugged this a bit and I think patch written by Tomi is partly
fixing this issue. It seems to be related to accessing cm_*
registers while there is transition ongoing in pwrdm_*. I
changed test_init to emulate what ckfw is currently doing:
static int __init test_init(void)
{
struct clk *c1 = clk_get(NULL, "dss_ick");
while(1) {
/* clk_enable(c1); */
/* clk_disable(c1); */
/* Add sleep and wkdeps */
omap_writel(0x2, 0x48004e44);
omap_writel(0x2, 0x48306ec8);
/* Enable dss_ick */
omap_writel(0x1, 0x48004e10);
/* disable dss_ick */
omap_writel(0x0, 0x48004e10);
/* Remove sleep and wkdeps */
omap_writel(0x0, 0x48004e44);
omap_writel(0x0, 0x48306ec8);
}
return 0;
}
This code crashes, but if I remove sleep/wkdep addition/removel from
the code it doesn't. It doesn't crash either if I add
"while((omap_readl(0x48306ee4)&0x100000));" after sleep/wkdep
addition/removel.
So it seems that cm_* register should not be written while there is
powerstate transition ongoing in * domain. Patch by Tomi is fixing
this. As it seems to be transition related rather than pwrdm state,
same line should be added into omap2_clkdm_clk_disable also.
>
> The following change waits until the powerdomain has finished the
> transition. At least it fixed the problem for me, and other things seem
> to be still working =).
>
>
> diff --git a/arch/arm/mach-omap2/clockdomain.c
> b/arch/arm/mach-omap2/clockdomain.c
> index fa62f14..f713d0b 100644
> --- a/arch/arm/mach-omap2/clockdomain.c
> +++ b/arch/arm/mach-omap2/clockdomain.c
> @@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
> struct clk *clk)
> else
> omap2_clkdm_wakeup(clkdm);
>
> + pwrdm_wait_transition(clkdm->pwrdm.ptr);
> +
> return 0;
> }
>
>
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--
Jouni Högander
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